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| SPICE Device Model SI7922DN Vishay Siliconix Dual N-Channel 100-V (D-S) MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70322 S-60245Rev. B, 20-Feb-06 www.vishay.com 1 SPICE Device Model SI7922DN Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 2.6 29 0.16 0.18 4.8 0.73 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 A VDS 5 V, VGS = 10 V VGS = 10 V, ID = 2.5 A VGS = 6 V, ID = 2.3 A VDS = 10 V, ID = 2.5 A IS = 2.2 A, VGS = 0 V V A 0.16 0.19 5.3 0.8 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea b Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = 2.2 A, di/dt = 100 A/s VDD = 50 V, RL = 50 ID 1 A, VGEN = 4.5 V, RG = 6 VDS = 50 V, VGS = 10 V, ID = 2.5 A 4.8 1.1 1.9 7 14 8 13 32 5.2 1.1 1.9 7 11 8 11 40 ns nC Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70322 S-60245Rev. B, 20-Feb-06 SPICE Device Model SI7922DN Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70322 S-60245Rev. B, 20-Feb-06 www.vishay.com 3 |
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